6-Axis IMU
ST LSM6DS3 — 3-axis accelerometer + 3-axis gyroscope. Shared I²C at 0x6A. Motion interrupt on GPIO 4 for wake-on-motion, tap detection, and free-fall.
OPEN HARDWARE // SOLANA ECOSYSTEM
ESPSOL
DevKit
Coin-sized Solana hardware.
Tamper-resistant by design.
A 40.6 mm circular ESP32-S3 board with on-board SE050 secure element, 6-axis IMU, PDM microphone, dual-mode USB-C, and Li-Po charging — all on a 2-layer PCB the size of a coin.
40.6 mm
Circular PCB
ESP32-S3
Dual-Core LX7
SE050
Secure Element
6-Axis
IMU (LSM6DS3)
Li-Po
Onboard Charging
CERN-OHL
Open Hardware
THE CORE
ESP32-S3.
Dual-core LX7.
The ESPSOL packs an ESP32-S3-WROOM-1-N16R8 module — 16 MB flash, 8 MB octal PSRAM — onto a 40.6 mm circular board. Wi-Fi 802.11 b/g/n and Bluetooth LE 5 ship built-in with no external antenna required.
Designed around Solana signing workflows, BLE-based transaction confirmation, and DePIN sensor attestation — all from a device smaller than a coin.
MCU MODULE
ESP32-S3
SE050C2HQ1
NXP EdgeLock
Secure · 0x48 on shared I²C
SECURE ELEMENT
Keys that never
leave silicon.
The NXP SE050 EdgeLock secure element performs all cryptographic operations inside tamper-resistant hardware. Private keys are generated and stored inside the element — they are never exposed to the ESP32-S3 application processor, not during Solana transaction signing, not ever.
The SE050 shares the onboard I²C bus (GPIO 9/10, address 0x48) with the IMU, and is held in reset via GPIO 5 until the firmware is ready to authenticate.
ONBOARD PERIPHERALS
Everything in 40 mm.
Nothing left out.
IMU, microphone, buzzer, USB bridge, battery charging, and user buttons — all integrated on the circular 2-layer board with no satellite boards required.
PDM Microphone
Knowles SPH0641LM4H-1 MEMS mic. Clock on GPIO 12, data on GPIO 11. I²S PDM-RX mode. Use for wake-word detection, voice-activated Solana actions, or audio attestation.
Magnetic Buzzer
KSSG33J12-3 buzzer driven by an SS8050 transistor via GPIO 48. PWM/LEDC at ~2.7 kHz resonance. Approval beeps for transaction signing.
USB-C Dual Mode
FSUSB42 MUX routes the single USB-C port to either native ESP32-S3 USB (HID/JTAG) or the CH340C UART bridge. GPIO 13 selects the path.
Li-Po Charging
MCP73831 charge controller + DW03D protection IC + AO3401A power-path MOSFET. Auto-selects USB vs battery. Red/blue LEDs for charging/full status.
User Buttons
Three tactile switches (SW1–GPIO 47, SW2–GPIO 21, SW3–GPIO 1) plus RST (EN) and BOOT (GPIO 0) for download mode. Active-low with internal pull-up.
USB DUAL MODE
One port.
Two personalities.
A single USB-C connector serves two completely different roles depending on what your firmware needs. The FSUSB42 2:1 multiplexer routes USB data lines to either the ESP32-S3's native USB PHY or the CH340C UART bridge — switched in firmware with GPIO 13.
Native USB mode enumerates as an HID device or USB-Serial-JTAG debugger. UART mode gives you a familiar serial console via CH340C. Flip the path at boot or at runtime without reconnecting.
FSUSB42 USB MUX
USB-C
SRV05-4 ESD
FSUSB42
GPIO 13 selects
LOW
Native USB
HID · JTAG
GPIO 19/20
GPIO 19/20
HIGH
CH340C UART
Serial console
GPIO 43/44
GPIO 43/44
POWER SYSTEM
USB or battery.
Protected either way.
The ESPSOL accepts power from USB-C (5V) or a single-cell Li-Po battery via the MX1.25 connector. An AO3401A P-MOSFET power path automatically selects the live source and feeds VSYS — the unregulated rail available on the J4 header.
A ME6211C33M5 LDO steps VSYS down to a regulated 3.3V for all digital logic. Battery voltage is monitored on GPIO 3 via a 22kΩ/22kΩ divider — read ADC1, multiply by 2 for actual cell voltage.
POWER ARCHITECTURE
USB-C 5V
Li-Po J1
MCP73831
Li-Po charger
DW03D
Battery protection
AO3401A
Auto power-path → VSYS
VSYS
J4 pin 2 · unregulated
3.3V
ME6211 500mA LDO
BATTERY MONITOR
GPIO 3 · ADC1 · 22k/22k divider · ×2 = Vcell
SOLANA USE CASES
Six ways to build
on Solana hardware.
The ESPSOL's secure element, wireless connectivity, audio I/O, and pocketable form factor unlock a range of Solana-native hardware applications right out of the box.
01
Hardware Wallet
Store private keys inside the SE050. Confirm Solana transactions with the three user buttons. The buzzer beeps on approval — keys never touch the host machine.
02
USB Authenticator
Enumerate as a USB HID device. Sign Solana transactions or 2FA challenges directly from the host via native USB — no drivers, no bridge.
03
Solana Pay Terminal
Compact Wi-Fi point-of-sale that generates Solana Pay payment requests. Add a display or reader to the GPIO headers for a complete checkout experience.
04
DePIN / IoT Node
Report IMU motion data, mic audio, or custom sensor readings to Solana programs. The SE050 provides hardware device identity for signed, tamper-proof attestations.
05
Voice-Triggered Wallet
Capture wake words or voice commands via the PDM microphone. Process locally on ESP32-S3 and trigger on-chain Solana actions without any button press.
06
Wearable Fob
Coin-sized, battery-powered, and pocketable. Clip it to a badge lanyard or wristband. Li-Po charging keeps it topped up between uses.
OPEN HARDWARE
KiCad source.
CERN-OHL-S v2.
The full KiCad project — schematic, PCB layout, and interactive BOM — is published under the CERN Open Hardware Licence v2 Strongly Reciprocal. Use it, fork it, manufacture it. Derivatives must remain open under the same terms.
github.com/SkyRizzAI/SkyRizz-ESPSOL →
SkyRizzAI / SkyRizz-ESPSOL
- DIR hardware/
- ├── SkyRizzESPSOL.kicad_pro
- ├── SkyRizzESPSOL.kicad_sch
- ├── SkyRizzESPSOL.kicad_pcb
- └── bom/ibom.html
- DIR assets/
- └── board renders
- FILE LICENSE.md
- FILE README.md
GET THE ESPSOL